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Virtex-II Platform FPGAs:
Pinout Information
DS031-4 (v4.0) April 7, 2014
Product Specification
This document provides Virtex-II™ Device/Package Combi-
nations, Maximum I/Os Available, and Virtex-II Pin Defini-
tions, followed by pinout tables for the following packages:
•
•
•
•
•
BG728/BGG728 Standard BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
BF957 Flip-Chip BGA Package
•
•
•
•
•
CS144/CSG144 Chip-Scale BGA Package
FG256/FGG256 Fine-Pitch BGA Package
FG456/FGG456 Fine-Pitch BGA Package
FG676/FGG676 Fine-Pitch BGA Package
BG575/BGG575 Standard BGA Package
For device pinout diagrams and layout guidelines, refer to
the Virtex-II Platform FPGA User Guide. ASCII package
pinout files are also available for download from the Xilinx
website (www.xilinx.com).
Virtex-II Device/Package Combinations and Maximum I/Os Available
Wire-bond and flip-chip packages are available. Table 1 and
Table 2 show the maximum number of user I/Os possible in
wire-bond and flip-chip packages, respectively.
•
FGG denotes Pb-free wire-bond fine-pitch BGA (1.00
mm pitch).
BG denotes standard BGA (1.27 mm pitch).
BGG denotes Pb-free standard BGA (1.27 mm pitch).
FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
BF denotes flip-chip BGA (1.27 mm pitch).
•
•
•
•
Table 3 shows the number of user I/Os available for all
device/package combinations.
•
•
•
CS denotes wire-bond chip-scale ball grid array (BGA)
(0.80 mm pitch).
CSG denotes Pb-free wire-bond chip-scale ball grid
array (BGA) (0.80 mm pitch).
The number of I/Os per package include all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, AND RSVD).
FG denotes wire-bond fine-pitch BGA (1.00 mm pitch).
Table 1: Wire-Bond Packages Information
CS144/
CSG144
FG256/
FGG256
FG456/
FGG456
FG676/
FGG676
BG575/
BGG575
BG728/
BGG728
(1)
Package
Pitch (mm)
0.80
12 x 12
92
1.00
1.00
23 x 23
324
1.00
27 x 27
484
1.27
31 x 31
408
1.27
35 x 35
516
Size (mm)
I/Os
17 x 17
172
Notes:
1. Wire-bond packages include FGGnnn Pb-free versions. See Virtex-II Ordering Examples (Module 1).
Table 2: Flip-Chip Packages Information
Package
Pitch (mm)
FF896
1.00
FF1152
1.00
FF1517
1.00
BF957
1.27
40 x 40
684
Size (mm)
I/Os
31 x 31
624
35 x 35
824
40 x 40
1,108
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trademarks are the property of their respective owners.
DS031-4 (v4.0) April 7, 2014
Product Specification
www.xilinx.com
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