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XC2S200E-6FG456I 参数 Datasheet PDF下载

XC2S200E-6FG456I图片预览
型号: XC2S200E-6FG456I
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE 1.8V FPGA系列 [Spartan-IIE 1.8V FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 4 页 / 113 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE 1.8V FPGA Family: Introduction and Ordering Information  
Spartan-IIE FPGAs achieve high-performance, low-cost  
operation through advanced architecture and semiconduc-  
tor technology. Spartan-IIE devices provide system clock  
rates beyond 200 MHz. Spartan-IIE FPGAs offer the most  
cost-effective solution while maintaining leading edge per-  
formance. In addition to the conventional benefits of  
high-volume programmable logic solutions, Spartan-IIE  
FPGAs also offer on-chip synchronous single-port and  
dual-port RAM (block and distributed form), DLL clock driv-  
ers, programmable set and reset on all flip-flops, fast carry  
logic, and many other features.  
General Overview  
The Spartan-IIE family of FPGAs have a regular, flexible,  
programmable architecture of Configurable Logic Blocks  
(CLBs), surrounded by a perimeter of programmable  
Input/Output Blocks (IOBs). There are four Delay-Locked  
Loops (DLLs), one at each corner of the die. Two columns  
of block RAM lie on opposite sides of the die, between the  
CLBs and the IOB columns. These functional elements are  
interconnected by a powerful hierarchy of versatile routing  
channels (see Figure 1).  
Spartan-IIE FPGAs are customized by loading configura-  
tion data into internal static memory cells. Unlimited repro-  
gramming cycles are possible with this approach. Stored  
values in these cells determine logic functions and intercon-  
nections implemented in the FPGA. Configuration data can  
be read from an external serial PROM (master serial mode),  
or written into the FPGA in slave serial, slave parallel, or  
Boundary Scan modes. The Xilinx XC17S00A PROM family  
is recommended for serial configuration of Spartan-IIE  
FPGAs. The XC18V00 reprogrammable PROM family is  
recommended for parallel or serial configuration.  
Spartan-IIE Family Compared to Spartan-II  
Family  
Higher density and more I/O  
Higher performance  
Unique pinouts in cost-effective packages  
Differential signaling  
-
LVDS, Bus LVDS, LVPECL  
= 1.8V  
V
CCINT  
-
-
-
Lower power  
5V tolerance with 100external resistor  
3V tolerance directly  
Spartan-IIE FPGAs are typically used in high-volume appli-  
cations where the versatility of a fast programmable solution  
adds benefits. Spartan-IIE FPGAs are ideal for shortening  
product development cycles while offering a cost-effective  
solution for high volume production.  
PCI, LVTTL, and LVCMOS2 input buffers powered by  
instead of V  
V
CCO  
CCINT  
Unique larger bitstream  
DLL  
DLL  
DLL  
DLL  
I/O LOGIC  
DS077_01_102201  
Figure 1: Basic Spartan-IIE Family FPGA Block Diagram  
2
www.xilinx.com  
DS077-1 (v1.0) November 15, 2001  
1-800-255-7778  
Preliminary Product Specification  
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