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Spartan-II 2.5V FPGA Family:
Introduction and Ordering
Information
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DS001-1 (v2.3) November 1, 2001
Preliminary Product Specification
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System level features
Introduction
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SelectRAM+™ hierarchical memory:
The Spartan™-II 2.5V Field-Programmable Gate Array fam-
ily gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System perfor-
mance is supported up to 200 MHz.
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16 bits/LUT distributed RAM
Configurable 4K bit block RAM
Fast interfaces to external RAM
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Fully PCI compliant
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
Spartan-II devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined Virtex-based architec-
ture. Features include block RAM (to 56K bits), distributed
RAM (to 75,264 bits), 16 selectable I/O standards, and four
DLLs. Fast, predictable interconnect means that successive
design iterations continue to meet timing requirements.
The Spartan-II family is
a
superior alternative to
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Versatile I/O and packaging
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
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Low cost packages available in all densities
Family footprint compatibility in common packages
16 high-performance interface standards
Hot swap Compact PCI friendly
Zero hold time simplifies system timing
Features
Fully supported by powerful Xilinx development system
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Foundation ISE Series: Fully integrated software
Alliance Series: For use with third-party tools
Fully automatic mapping, placement, and routing
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Second generation ASIC replacement technology
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Densities as high as 5,292 logic cells with up to
200,000 system gates
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Streamlined features based on Virtex architecture
Unlimited reprogrammability
Very low cost
Table 1: Spartan-II FPGA Family Members
CLB
Array
(R x C)
Maximum
Available
User I/O
Total
Distributed RAM
Bits
Total
Block RAM
Bits
Logic
Cells
System Gates
(Logic and RAM)
Total
CLBs
(1)
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
432
972
15,000
30,000
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
96
86
6,144
13,824
24,576
38,400
55,296
75,264
16K
24K
32K
40K
48K
56K
216
132
176
196
260
284
1,728
2,700
3,888
5,292
50,000
384
100,000
150,000
200,000
600
864
1,176
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS001-1 (v2.3) November 1, 2001
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
