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W1D32M72R8A-5AR-QB1 参数 Datasheet PDF下载

W1D32M72R8A-5AR-QB1图片预览
型号: W1D32M72R8A-5AR-QB1
PDF下载: 下载PDF文件 查看货源
内容描述: [32MX8 DDR DRAM MODULE, 0.6ns, DMA240, MO-237, DIMM-240]
分类和应用: 动态存储器双倍数据速率内存集成电路
文件页数/大小: 11 页 / 256 K
品牌: XILINX [ XILINX, INC ]
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DDR2-400, 533  
Single Rank, x8 Registered SDRAM DIMMs  
Electrical Characteristics and AC Timings:  
VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C<TOPR <+55°C, VOUT(DC) = VDDQ/2  
Symbol  
-5  
-3.75  
Units  
Parameter  
DDR2-400  
DDR2-533  
MIN  
MAX  
MIN  
MAX  
tAC  
-600  
-500  
+600  
-500  
-450  
+500 ps  
+450 ps  
DQ output access time from CK/  
CK  
tDQSCK  
+500  
DQS output access time from CK/  
CK  
CK high-level width  
CK low-level width  
CK half period  
tCH  
tCL  
tHP  
0.45  
0.45  
0.55  
0.55  
-
0.45  
0.45  
0.55  
0.55  
-
tCK  
tCK  
ps  
MIN  
(tCH,  
tCL)  
MIN  
(tCH,  
tCL)  
Clock cycle time  
tCK CL=3  
5,000  
CL=4 & 5 5,000  
8,000  
8,000  
5,000  
3,750  
8,000 ps  
8,000 ps  
DQ and DM input hold time  
DQ and DM input setup time  
tDH  
tDS  
400  
400  
0.6  
-
-
-
350  
350  
0.6  
-
-
-
ps  
ps  
Control & Address input pulse width for tIPW  
tCK  
each input  
DQ and DM input pulse width for each tDIPW  
input  
0.35  
-
0.35  
-
tCK  
ps  
-
tACmax  
-
tACmax  
Data-out high-impedance time from  
tHZ  
CK/  
CK  
Data-out low-impedance time from  
CK/  
tACmin  
tACmax  
tACmin  
tACmax  
tLZ  
ps  
ps  
CK  
DQS-DQ skew for DQS and associated DQ tDQSQ  
signals  
-
350  
-
300  
Data hold skew factor  
tQHS  
tQH  
-
450  
-
-
400  
-
ps  
ps  
Data output hold time from DQS  
tHP-  
tHP-  
tQHS  
WL-0.25  
tQHS  
WL-0.25  
Write command to 1st DQS latching  
transition  
DQS input low/high pulse width  
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
tDQSS  
WL+  
0.25  
-
-
-
-
WL+ tCK  
0.25  
tDQSL/H  
tDSS  
0.35  
0.2  
0.2  
2
0.35  
0.2  
0.2  
2
-
-
-
-
tCK  
tCK  
tCK  
tCK  
tDSH  
Mode register set command cycle time tMRD  
Write preamble setup time  
Write preamble  
tWPRES  
0
-
0
-
-
ps  
tWPRE  
tWPST  
tRPRE  
tRPST  
tRAS  
tRC  
0.25  
0.40  
0.9  
0.4  
45  
-
0.25  
0.40  
0.9  
0.4  
45  
tCK  
tCK  
tCK  
tCK  
Write postamble  
0.60  
0.60  
1.1  
0.6  
Read preamble  
Read postamble  
Active to Precharge command  
Active to Active command period  
Refresh to Refresh command interval  
Active to Read/Write delay  
Precharge command period  
1.1  
0.6  
70,000  
70,000 ns  
60  
-
-
-
-
60  
-
-
-
-
ns  
ns  
ns  
ns  
tRFC  
tRCD  
tRP  
105  
15  
105  
15  
15  
15  
DDR2_RDIMM_1 rank_x8_spec  
Rev. 1.0 - December, 04  
Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  
2004 Wintec Industries, Inc.  
7
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