W1D128M72R8B-5AR-FA1 参数 Datasheet PDF下载

DDR2-400, 533

Single Rank, x8 Registered SDRAM DIMMs

Functional Block Diagram:

Single Rank 32M x 72 (256MB), 64M x 72 (512MB), 128M x 72 (1GB), and 256M x 72 (2GB) DDR2 Registered

SDRAM DIMM (x8 organization)

RCS0#

DQS0

DQS0#

DM0/DQS9

DQS9#

DQ[0:7]

8

DQS1

DQS1#

DM1/DQS10

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

DQS4

DQS4#

DM4/DQS13

DQS13#

DQ[32:39]

8

DQS5

DQS5#

DM5/DQS14

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

U0

U4

DQS10#

DQ[8:15]

8

DQS2

DQS2#

DM2/DQS11

DQS14#

DQ[40:47]

8

DQS6

DQS6#

DM6/DQS15

U1

U5

DQS11#

DQ[16:23]

8

DQS3

DQS3#

DM3/DQS12

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

DQS15#

DQ[48:55]

8

DQS7

DQS7#

DM7/DQS16

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

U2

U6

DQS12#

DQ[24:31]

8

DQS8

DQS8#

DM8/DQS17

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

DQS16#

DQ[56:63]

8

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

U3

U7

DQS17#

CB[0:7]

8

NU/

DM/ CS# DQS# DQS

RDQS# RDQS

V

DDSPD

V

DD

/V

DDQ

V

REF

Vss

SERIAL PD

SCL

A0

SA0

A1

SA1

A2

SA2

U8

To SPD

To U0 - U8

To U0 - U8

To U0 - U8

SDA

BA0-BA1

A0-A13

RAS#

CAS#

WE#

CKE0

ODT0

CS0#*

RESET#

R

E

G

I

S

T

E

R

RST#

RBA0-RBA1 -> BA0-BA1 to U0 - U8

RA0-RA13 -> A0-A13 to U0 - U8

RRAS# -> RAS# to U0 - U8

RCAS# -> CAS# to U0 - U8

RWE# -> WE# to U0 - U8

RCKE0 -> CKE0 to U0 - U8

RODT0 -> ODT0 to U0 - U8

RS0# -> CS0# to U0 - U8

CK0

CK0#

RESET#

P

L

L

CK to U0 - U8

CK# to U0 - U8

CK to all registers

CK# to all registers

Note:

1. *) CS0# connects to DCS# of Register 1 and CSR# of Register 2;

CSR# of Register 1 and DCS# of Register 2 connects to VDD

2. DQ/DM/DQS, address and control resistor values are 22 Ohms.

DDR2_RDIMM_1 rank_x8_spec

Rev. 1.0 - December, 04

Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.



2004 Wintec Industries, Inc.

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