Philips Semiconductors
Preliminary specification
320 macrocell SRAM CPLD
PZ3320C/PZ3320N
XPLA2 Logic Block Architecture
Figure 3 illustrates the XPLA2 Logic Block architecture. Each Logic
Block contains 8 control terms, a PAL array, a PLA array, and 20
macrocells. The 36 inputs from the LZIA are available to all control
terms and to each product term in both the PAL and the PLA array.
The 8 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the asynchronous preset
and reset functions of the macrocell registers, the output enables of
the 20 macrocells, and for asynchronous clocking. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array.
Each macrocell has 4 dedicated product terms from the PAL array.
When additional logic is required, each macrocell takes the extra
product terms from the PLA array. The PLA array consists of 32
extra product terms that are shared between the 20 macrocells of
the Logic Block. The PAL product terms can be connected to the
PLA product terms through either an OR gate or an XOR gate. One
input to the XOR gate can be connected to all the PLA terms, which
provides for extremely efficient logic synthesis. An eight bit XOR
function can be implemented in only 20 product terms. Each
macrocell can use the output from the OR gate or the XOR gate in
either normal or inverted state.
LZIA
INPUTS
36
CONTROL
4
8
MC0
4
MC1
4
PAL
ARRAY
MC2
4
MC19
PLA
ARRAY
(32)
PATENT PENDING
SP00589A
Figure 3. Philips XPLA2 Logic Block Architecture
1998 Jul 22
6
XILINX [ XILINX, INC ]
