MT9040
Data Sheet
Reset Circuit
A simple power up reset circuit with about a 50 us reset low time is shown in Figure 7. Resistor R is for protection
P
only and limits current into the RST pin during power down conditions. The reset low time is not critical but should
be greater than 300 ns.
MT9040
+3.3 V
R
10 kΩ
RST
RP
1 kΩ
C
10 nF
Figure 7 - Power-Up Reset Circuit
Lock Indicator
The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. The low time
totally depends on the spectral content of jitter/wander that is present on the input reference and the 20 MHz
system clock of the MT9040.
If the reference clock input is within +/-100ppm, the low state on the LOCK pin would not exceed 30sec. If the
LOCK state remains low for more than 30sec, it indicates that the MT9040 is not able to maintain lock to the
incoming reference. In the event that the reference clock from the network is missing, the MT9040 will be in the
Freerun mode.
Flock should only be use at powerup, otherwise the output clock will not meet AT&T TR62411 and Bellcore GR-
1244-CORE and Stratum 4 timing standard.
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Zarlink Semiconductor Inc.
XILINX [ XILINX, INC ]
