MT9040
T1/E1 Synchronizer
Data Sheet
Features
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•
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Supports AT&T TR62411 and Bellcore GR-1244-
CORE and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or
8kHz input reference signals
Provides C1.5, C2, C4, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9 Hz
Fast lock mode
JTAG Boundary Scan
Ordering Information
MT9040AN
48 Pin SSOP
MT9040ANR
48 Pin SSOP
MT9040AN1
48 Pin SSOP*
MT9040ANR1 48 Pin SSOP*
*Pb Free Matte Tin
-40°C to +85°C
Tubes
Tape & Reel
Tubes
Tape & Reel
February 2009
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for T1 and E1 primary rate
transmission links.
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048 MHz, 1.544 MHz, or 8 kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and capture
range for these specifications.
LOCK
VDD
VSS
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•
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Applications
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•
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse source
OSCi
OSCo
FLOCK
Master Clock
TCK
TDI
TMS
TRST
TDO
IEEE
1149.1a
DPLL
Output
Interface
Circuit
Input
Impairment
Monitor
REF
C19o
C1.5o
C2o
C4o
C6o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
Control State Machine
Feedback
Frequency
Select
MUX
MS
RST
IM
FS1
FS2
Figure 1 - Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2009, Zarlink Semiconductor Inc. All Rights Reserved.
XILINX [ XILINX, INC ]
