R
Platform Flash XL High-Density Configuration and Storage Device
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Revision
12/13/07
03/31/08
Initial Xilinx release.
2.0
Added bus operations and advance device specifications:
• Expanded "Command Interface," page 14, adding new sections.
• Added the following sections:
♦ "Status Register," page 23
♦ "Configuration Register," page 26
♦ "Read Modes," page 34
♦ "Dual Operations and Multiple Bank Architecture," page 35
♦ "Block Locking," page 37
♦ "Power-On Reset," page 39
♦ "First Address Latching Sequence," page 41
♦ "Program and Erase Times and Endurance Cycles," page 44
♦ "Maximum Rating," page 45
♦ "DC and AC Parameters," page 45
♦ "Appendix A: Block Address Tables," page 61
♦ "Appendix B: Common Flash Interface," page 65
♦ "Appendix C: Flowcharts and Pseudocodes," page 71
♦ "Appendix D: Command Interface State Tables," page 80
Other corrections and updates:
• Corrected resistor values in Figure 7, page 10.
• Corrected resistor values and removed external resistors from signal K in Figure 8, page 11.
• Updated "Marking Information," page 61.
05/14/08
2.1
• Data sheet status changed from Advance to Preliminary.
• Corrected the nomenclature for the FT64 package.
• Replaced section “FPGA Master BPI-Up Configuration Mode.” with section "Alternate Configuration
Modes," page 11.
• Updated Figure 18, page 40 with annotations for TVDDPOR
• Updated Table 21, page 44 to show correct values of VPP.
• Updated Table 31, page 58.
.
• Updated trademark references.
10/29/08
2.2
• Minor corrections throughout.
• Updated Figure 1, page 2, Figure 7, page 12, Figure 8, page 22, Figure 12, page 31, Figure 15,
page 33, Figure 17, page 39, Figure 18, page 40, and Figure 24, page 46.
• Updated Figure 14, page 32, Figure 16, page 33, Figure 20, page 42, Figure 33, page 58, and
Figure 34, page 59 to reflect changed timing parameter nomenclature.
• Added maximum rating for junction temperature to Table 22, page 45.
• Added Table 24, page 46.
• Updated Table 2, page 6, Table 4, page 9, Table 9, page 21, Table 21, page 44, and Table 44,
page 69.
• Added new voltage range information to Table 28, page 50.
• Updated Table 32, page 59 to reflect changed timing parameter nomenclature.
• Updated Table 19, page 42, Table 20, page 43, Table 29, page 52, Table 30, page 56, Table 31,
page 58, and Table 33, page 60. (Added new voltage range information and updated tables to
reflect changed timing parameter nomenclature.)
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
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