R
Functional Description
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 24.
Table 24: Block RAM Attributes
Function
Attribute
INITxx
Possible Values
Initial Content for Data Memory, Loaded
during Configuration
Each initialization string defines 32 hex values of
(INIT_00 through INIT3F) the 16384-bit data memory of the block RAM.
Initial Content for Parity Memory, Loaded
during Configuration
INITPxx Each initialization string defines 32 hex values of
(INITP_00 through INITP0F) the 2048-bit parity data memory of the block
RAM.
Data Output Latch Initialization
INIT(single-port)
Hex value the width of the chosen port.
INITA, INITB(dual-port)
Data Output Latch Synchronous
Set/Reset Value
SRVAL(single-port)
SRVAL_A, SRVAL_B
(dual-port)
Hex value the width of the chosen port.
Data Output Latch Behavior during Write
WRITE_MODE
WRITE_FIRST, READ_FIRST, NO_CHANGE
(see Block RAM Data Operations)
The waveforms for the write operation are shown in the top
half of Figure 33, Figure 34, and Figure 35. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 25 describes the data opera-
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
Table 25: Block RAM Function Table
Input Signals
Output Signals
RAM Data
Parity
GSR EN SSR WE CLK ADDR
Immediately After Configuration
Loaded During Configuration
DIP
DI
DOP
DO
Data
X
X
INITP_xx
No Chg
No Chg
No Chg
INIT_xx
No Chg
No Chg
No Chg
Global Set/Reset Immediately After Configuration
1
0
0
0
X
0
1
1
X
X
1
1
X
X
0
1
X
X
X
X
X
X
X
INIT
RAM Disabled
No Chg
INIT
X
X
No Chg
Synchronous Set/Reset
SRVAL
↑
X
X
SRVAL
Synchronous Set/Reset During Write RAM
↑
↑
addr
pdata Data
SRVAL
SRVAL
RAM(addr)
RAM(addr)
← pdata
← data
Read RAM, no Write Operation
RAM(pdata)
0
1
0
0
addr
X
X
RAM(data)
No Chg
No Chg
40
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DS312-2 (v3.8) August 26, 2009
Product Specification
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