R
Pinout Descriptions
PQ208: 208-pin Plastic Quad Flat Package
The 208-pin plastic quad flat package, PQ208, supports two
different Spartan-3E FPGAs, including the XC3S250E and
the XC3S500E.
Table 141: PQ208 Package Pinout (Continued)
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Type
I/O
Table 141 lists all the PQ208 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
IO_L15P_0
P202
P206
P205
P159
P169
P194
P204
P175
P174
P184
P183
P176
P191
P201
P107
P106
P109
P108
P113
P112
P116
P115
P120
P119
P123
P122
IO_L16N_0/HSWAP
IO_L16P_0
DUAL
I/O
IP
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
VCCO
VCCO
VCCO
DUAL
DUAL
DUAL
DUAL
VREF
I/O
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at:
IP
IP
http://www.xilinx.com/support/documentation/data_sheets/s3e_pin.zip.
IP
IP_L06N_0
Pinout Table
IP_L06P_0
Table 141: PQ208 Package Pinout
IP_L09N_0/GCLK9
IP_L09P_0/GCLK8
VCCO_0
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Bank
0
Type
I/O
VCCO_0
IO
P187
P179
P161
P160
P163
P162
P165
P164
P168
P167
P172
P171
P178
P177
P181
P180
P186
P185
P190
P189
P193
P192
P197
P196
P200
P199
P203
VCCO_0
0
IO/VREF_0
VREF
I/O
IO_L01N_1/A15
IO_L01P_1/A16
IO_L02N_1/A13
IO_L02P_1/A14
IO_L03N_1/VREF_1
IO_L03P_1
0
IO_L01N_0
0
IO_L01P_0
I/O
0
IO_L02N_0/VREF_0
IO_L02P_0
VREF
I/O
0
0
IO_L03N_0
I/O
0
IO_L03P_0
I/O
IO_L04N_1
I/O
0
IO_L04N_0/VREF_0
IO_L04P_0
VREF
I/O
IO_L04P_1
I/O
0
IO_L05N_1/A11
IO_L05P_1/A12
IO_L06N_1/VREF_1
IO_L06P_1
DUAL
DUAL
VREF
I/O
0
IO_L05N_0
I/O
0
IO_L05P_0
I/O
0
IO_L07N_0/GCLK5
IO_L07P_0/GCLK4
IO_L08N_0/GCLK7
IO_L08P_0/GCLK6
IO_L10N_0/GCLK11
IO_L10P_0/GCLK10
IO_L11N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
IO_L07N_1/A9/RHCLK1
IO_L07P_1/A10/RHCLK0
IO_L08N_1/A7/RHCLK3
IO_L08P_1/A8/RHCLK2
IO_L09N_1/A5/RHCLK5
IO_L09P_1/A6/RHCLK4
IO_L10N_1/A3/RHCLK7
IO_L10P_1/A4/RHCLK6
IO_L11N_1/A1
IO_L11P_1/A2
IO_L12N_1/A0
IO_L12P_1
P127 RHCLK/DUAL
P126 RHCLK/DUAL
P129 RHCLK/DUAL
P128 RHCLK/DUAL
P133 RHCLK/DUAL
P132 RHCLK/DUAL
P135 RHCLK/DUAL
P134 RHCLK/DUAL
0
0
0
0
0
0
IO_L11P_0
I/O
0
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
0
P138
P137
P140
P139
P145
DUAL
DUAL
DUAL
I/O
0
IO_L13N_0
I/O
0
IO_L13P_0
I/O
0
IO_L14N_0/VREF_0
IO_L14P_0
VREF
I/O
0
IO_L13N_1
I/O
0
IO_L15N_0
I/O
186
www.xilinx.com
DS312-4 (v3.8) August 26, 2009
Product Specification
XILINX [ XILINX, INC ]
