Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1)
Speed Grade
-3 -2
Symbol
Description
-4
-1L
Units
Min
Max
Min
Max
Min
Max
Min
Max
Output Frequency Ranges (DCM_CLKGEN)
CLKOUT_FREQ_FX
Frequency for the CLKFX and
CLKFX180 outputs
5
375
5
375
5
333
5
200 MHz
CLKOUT_FREQ_FXDV
Frequency for the CLKFXDV
output
0.15625 187.5 0.15625 187.5 0.15625 166.5 0.15625 100 MHz
(2)(3)
Output Clock Jitter
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and
CLKFX180 outputs.
Typical = [0.2% of CLKFX period + 100]
Typical = [0.2% of CLKFX period + 100]
ps
ps
CLKOUT_PER_JITT_FXDV Period jitter at the CLKFXDV
output.
CLKFX period change in free
running oscillator mode at the
same temperature.
Maximum = 3% of CLKFX period
Maximum = 5% of CLKFX period
ps
ps
FCLKFX > 50 MHz
CLKFX_FREEZE_VAR
CLKFX period change in free
running oscillator mode at the
same temperature.
FCLKFX < 50 MHz
CLKFX_FREEZE_TEMP
_SLOPE
CLKFX period will change in
free_oscillator mode over
temperature. Add to
CLKFX_FREEZE_VAR to
determine total CLKFX period
change. Percentage change for
CLKFX period over 1°C.
Maximum = 0.1
%/°C
(4)(5)
Duty Cycle
CLKOUT_DUTY_CYCLE_ Duty cycle precision for the
FX
CLKFX and CLKFX180 outputs,
including the BUFGMUX and
clock tree duty-cycle distortion
Maximum = [1% of CLKFX period + 350]
Maximum = [1% of CLKFX period + 350]
ps
ps
CLKOUT_DUTY_CYCLE_ Duty cycle precision for the
FXDV
CLKFXDV outputs, including the
BUFGMUX and clock tree
duty-cycle distortion
Lock Time
LOCK_FX(2)
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output.
The DFS asserts LOCKED when
the CLKFX, CLKFX180, and
CLKFXDV signals are valid.
–
–
50
–
–
50
–
–
50
–
–
50
ms
ms
Lock time requires
CLKFX_DIVIDE < FIN/(0.50
MHz)
when:
5 MHz < FCLKIN < 50 MHz
when:
FCLKIN > 50 MHz
5
5
5
5
DS162 (v1.9) August 23, 2010
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Advance Product Specification
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