R
Spartan-IIE FPGA Family: Functional Description
During start-up, the device performs four operations:
Default Cycles
1. The assertion of DONE. The failure of DONE to go High
may indicate the unsuccessful loading of configuration
data.
Start-up CLK
Phase
2. The release of the Global Three State (GTS). This
activates all the I/Os to which signals are assigned. The
remaining I/Os stay in a high-impedance state with
internal weak pull-up resistors present.
0
1
2
3
4
5
6 7
DONE
GTS
3. The release of the Global Set Reset (GSR). This allows
all flip-flops to change state.
4. The assertion of Global Write Enable (GWE). This
allows all RAMs and flip-flops to change state.
GSR
By default, these operations are synchronized to CCLK.
The entire start-up sequence lasts eight cycles, called
C0-C7, after which the loaded design is fully functional. The
four operations can be selected to switch on any CCLK
GWE
cycle
C1-C6
through
settings
in
the
Xilinx
Sync to DONE
Development Software. The default timing for start-up is
shown in the top half of Figure 17; heavy lines show default
settings.
Start-up CLK
Phase
0
1
2
3
4
5
6 7
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is
released. This permits device outputs to turn on as neces-
sary.
DONE High
DONE
GTS
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
GSR
The bottom half of Figure 17 shows another commonly
used version of the start-up timing known as
Sync-to-DONE. This version makes the GTS, GSR, and
GWE events conditional upon the DONE pin going High.
This timing is important for a daisy chain of multiple FPGAs
in serial mode, since it ensures that all FPGAs go through
start-up together, after all their DONE pins have gone High.
GWE
DS001_13_090600
Figure 17: Start-Up Waveforms
Serial Modes
Sync-to-DONE timing is selected by setting the GTS, GSR,
and GWE cycles to a value of DONE in the configuration
options. This causes these signals to transition one clock
cycle after DONE externally transitions High.
There are two serial configuration modes. In Master Serial
mode, the FPGA controls the configuration process by driv-
ing CCLK as an output. In Slave Serial mode, the FPGA
passively receives CCLK as an input from an external agent
(e.g., a microprocessor, CPLD, or second FPGA in master
mode) that is controlling the configuration process. In both
modes, the FPGA is configured by loading one bit per CCLK
cycle. The MSB of each configuration data byte is always
written to the DIN pin first.
The sequence can also be paused at any stage until lock
has been achieved on any or all DLLs.
See Figure 18 for the sequence for loading data into the
Spartan-IIE FPGA serially. This is an expansion of the
"Load Configuration Data Frames" block in Figure 16,
page 23. Note that CS and WRITE are not normally used
during serial configuration. To ensure successful loading of
the FPGA, do not toggle WRITE with CS Low during serial
configuration.
24
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DS077-2 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
