R
Spartan-IIE FPGA Family: Functional Description
Table 7 shows the depth and width aspect ratios for the
block RAM.
To Adjacent
GRM
Table 7: Block RAM Port Aspect Ratios
To
To Adjacent
GRM
Width
Depth
4096
2048
1024
512
ADDR Bus
ADDR<11:0>
ADDR<10:0>
ADDR<9:0>
ADDR<8:0>
ADDR<7:0>
Data Bus
DATA<0>
Adjacent
GRM
GRM
1
2
DATA<1:0>
DATA<3:0>
DATA<7:0>
DATA<15:0>
To Adjacent
GRM
4
Direct
Direct Connection
To Adjacent
CLB
8
CLB
Connection
To Adjacent
CLB
16
256
DS001_06_032300
The Spartan-IIE FPGA block RAM also includes dedicated
routing to provide an efficient interface with both CLBs and
other block RAMs. See Xilinx Application Note XAPP173 for
more information on block RAM.
Figure 9: Spartan-IIE Local Routing
General Purpose Routing
Most Spartan-IIE FPGA signals are routed on the general
purpose routing, and consequently, the majority of intercon-
nect resources are associated with this level of the routing
hierarchy. The general routing resources are located in hor-
izontal and vertical routing channels associated with the
rows and columns of CLBs. The general-purpose routing
resources are listed below.
Programmable Routing
It is the longest delay path that limits the speed of any
design. Consequently, the Spartan-IIE FPGA routing archi-
tecture and its place-and-route software were defined jointly
to minimize long-path delays and yield the best system per-
formance.
•
Adjacent to each CLB is a General Routing Matrix
(GRM). The GRM is the switch matrix through which
horizontal and vertical routing resources connect, and
is also the means by which the CLB gains access to
the general purpose routing.
The joint optimization also reduces design compilation
times because the architecture is software-friendly. Design
cycles are correspondingly reduced due to shorter design
iteration times.
The software automatically uses the best available routing
based on user timing requirements. The details are pro-
vided here for reference.
•
•
24 single-length lines route GRM signals to adjacent
GRMs in each of the four directions.
96 buffered Hex lines route GRM signals to other
GRMs six blocks away in each one of the four
directions. Organized in a staggered pattern, Hex lines
may be driven only at their endpoints. Hex-line signals
can be accessed either at the endpoints or at the
midpoint (three blocks from the source). One third of
the Hex lines are bidirectional, while the remaining
ones are unidirectional.
12 Longlines are buffered, bidirectional wires that
distribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of the
device, and horizontal ones span the full width of the
device.
Local Routing
The local routing resources, as shown in Figure 9, provide
the following three types of connections:
•
Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM), described below.
•
Internal CLB feedback paths that provide high-speed
connections to LUTs within the same CLB, chaining
them together with minimal routing delay
•
•
Direct paths that provide high-speed connections
between horizontally adjacent CLBs, eliminating the
delay of the GRM
I/O Routing
Spartan-IIE devices have additional routing resources
around their periphery that form an interface between the
CLB array and the IOBs. This additional routing, called the
VersaRing™ routing, facilitates pin-swapping and pin-lock-
ing, such that logic redesigns can adapt to existing PCB lay-
outs. Time-to-market is reduced, since PCBs and other
system components can be manufactured while the logic
design is still in progress.
16
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DS077-2 (v2.3) June 18, 2008
Product Specification
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