R
Spartan-IIE FPGA Family: Functional Description
T
SR
V
CCO
D
Q
Package
Pin
TFF
CLK
TCE
SR
CK
EC
V
OE
CC
I/O
Programmable
Bias and
ESD Network
Package Pin
SR
O
D
Q
Programmable
Output Buffer
OFF
CK
EC
Internal
Reference
(1)
CC
OCE
V
Programmable
Delay
IQ
I
I/O, V
REF
SR
Package Pin
Programmable
Input Buffer
D
Q
IFF
CK
EC
To Next I/O
ICE
To Other
External V
Inputs
REF
of Bank
Notes:
1. For some I/O standards.
DS077-2_01_051501
Figure 4: Spartan-IIE Input/Output Block (IOB)
Table 3: Standards Supported by I/O (Typical Values)
Input Output Board
Reference Input Source Termination
Voltage Voltage Voltage Voltage
Input/Output Block
The Spartan-IIE FPGA IOB, as seen in Figure 4, features
inputs and outputs that support a wide variety of I/O signal-
ing standards. These high-speed inputs and outputs are
capable of supporting various state of the art memory and
bus interfaces. The default standard is LVTTL. Table 3 lists
several of the standards which are supported along with the
required reference (VREF), output (VCCO) and board termi-
nation (VTT) voltages needed to meet the standard. For
more details on the I/O standards and termination applica-
tion examples, see XAPP179, "Using SelectIO Interfaces in
Spartan-II and Spartan-IIE FPGAs."
I/O Standard
LVTTL (2-24 mA)
LVCMOS2
(VREF
)
(VCCO
)
(VCCO
)
(VTT
N/A
N/A
N/A
N/A
)
N/A
3.3
3.3
N/A
2.5
2.5
LVCMOS18
N/A
1.8
1.8
PCI (3V,
N/A
3.3
3.3
33 MHz/66 MHz)
GTL
0.8
1.0
0.75
0.9
0.9
1.5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
3.3
1.2
1.5
GTL+
The three IOB registers function either as edge-triggered
D-type flip-flops or as level-sensitive latches. Each IOB has
a clock signal (CLK) shared by the three registers and inde-
pendent Clock Enable (CE) signals for each register.
HSTL Class I
HSTL Class III
HSTL Class IV
0.75
1.5
1.5
SSTL3 Class I
and II
1.5
In addition to the CLK and CE control signals, the three reg-
isters share a Set/Reset (SR). For each register, this signal
can be independently configured as a synchronous Set, a
synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
SSTL2 Class I
and II
1.25
N/A
2.5
1.25
CTT
1.5
1.32
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
2.5
3.3
1.5
N/A
N/A
N/A
AGP
A feature not shown in the block diagram, but controlled by
the software, is polarity control. The input and output buffers
and all of the IOB control signals have independent polarity
controls.
LVDS, Bus LVDS
LVPECL
10
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DS077-2 (v2.3) June 18, 2008
Product Specification
XILINX [ XILINX, INC ]
