R
Spartan and Spartan-XL FPGA Families Data Sheet
falling CCLK edge, and the next FPGA in the daisy chain
accepts data on the subsequent rising CCLK edge. See the
timing diagram in Figure 24.
Master Serial Mode
The Master serial mode uses an internal oscillator to gener-
ate a Configuration Clock (CCLK) for driving potential slave
devices and the Xilinx serial-configuration PROM
(SPROM). The CCLK speed is selectable as either 1 MHz
(default) or 8 MHz. Configuration always starts at the default
slow frequency, then can switch to the higher frequency dur-
ing the first frame. Frequency tolerance is –50% to +25%.
In the bitstream generation software, the user can specify
Fast Configuration Rate, which, starting several bits into the
first frame, increases the CCLK frequency by a factor of
eight. For actual timing values please refer to the specifica-
tion section. Be sure that the serial PROM and slaves are
fast enough to support this data rate. Earlier families such
as the XC3000 series do not support the Fast Configuration
Rate option.
In Master Serial mode, the CCLK output of the device drives
a Xilinx SPROM that feeds the FPGA DIN input. Each rising
edge of the CCLK output increments the Serial PROM inter-
nal address counter. The next data bit is put on the SPROM
data output, connected to the FPGA DIN pin. The FPGA
accepts this data on the subsequent rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user I/O, but LDC is then
restricted to be a permanently High user output after config-
uration. Using DONE can also avoid contention on DIN, pro-
vided the Early DONE option is invoked.
When used in a daisy-chain configuration the Master Serial
FPGA is placed as the first device in the chain and is
referred to as the lead FPGA. The lead FPGA presents the
preamble data, and all data that overflows the lead device,
on its DOUT pin. There is an internal pipeline delay of 1.5
CCLK periods, which means that DOUT changes on the
Figure 25 shows a full master/slave system. The leftmost
device is in Master Serial mode, all other devices in the
chain are in Slave Serial mode.
CCLK
(Output)
T
CKDS
T
DSCK
Serial Data In
n
n + 1
n + 2
Serial DOUT
(Output)
n – 3
n – 2
n – 1
n
DS060_24_080400
Symbol
TDSCK
Description
Min
20
0
Units
ns
DIN setup
DIN hold
CCLK
TCKDS
ns
Notes:
1. At power-up, VCC must rise from 2.0V to VCC min in less than 25 ms, otherwise
delay configuration by pulling PROGRAM Low until VCC is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 24: Master Serial Mode Programming Switching Characteristics
The lead FPGA then presents the preamble data—and all
data that overflows the lead device—on its DOUT pin. There
is an internal delay of 0.5 CCLK periods, which means that
DOUT changes on the falling CCLK edge, and the next
FPGA in the daisy chain accepts data on the subsequent
rising CCLK edge.
Slave Serial Mode
In Slave Serial mode, the FPGA receives serial configura-
tion data on the rising edge of CCLK and, after loading its
configuration, passes additional data out, resynchronized
on the next falling edge of CCLK.
In this mode, an external signal drives the CCLK input of the
FPGA (most often from a Master Serial device). The serial
configuration bitstream must be available at the DIN input of
the lead FPGA a short setup time before each rising CCLK
edge.
Figure 25 shows a full master/slave system. A Spartan/XL
device in Slave Serial mode should be connected as shown
in the third device from the left.
DS060 (v1.8) June 26, 2008
www.xilinx.com
27
Product Specification
XILINX [ XILINX, INC ]
