R
Virtex-II Platform FPGAs: Functional Description
Table 8: SelectI/O-Ultra Differential Buffers With On-Chip Termination
IOSTANDARD Attribute
On-Chip Termination
I/O Standard Description
LVDS 2.5V
LVDS Extended 2.5V
External Termination
LVDS_25
LVDS_25_DCI
LVDSEXT_25
LVDSEXT_25_DCI
Figure 11 provides examples illustrating the use of the HSTL_I_DCI, HSTL_II_DCI, HSTL_III_DCI, and HSTL_IV_DCI I/O
standards. For a complete list, see the Virtex-II Platform FPGA User Guide.
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
V
/2
V
/2
V
/2
V
V
V
CCO
CCO
CCO
CCO
CCO
CCO
R
R
R
R
R
R
Conventional
Z
Z
Z
0
Z
0
0
0
V
V
/2
CCO
V
/2
CCO
CCO
V
V
V
CCO
DCI Transmit
Conventional
Receive
CCO
CCO
R
2R
R
R
R
R
Z
Z
0
0
Z
Z
0
0
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
/2
V
V
CCO
CCO
2R
CCO
2R
V
V
V
Conventional
Transmit
DCI Receive
CCO
R
CCO
CCO
R
R
R
Z
Z
0
0
Z
Z
0
0
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
V
V
CCO
CCO
2R
CCO
V
V
CCO
V
CCO
CCO
R
2R
2R
DCI Transmit
DCI Receive
R
R
Z
Z
0
0
Z
Z
0
0
2R
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
V
V
V
V
CCO
CCO
CCO
CCO
R
2R
R
2R
Z
Z
0
0
Bidirectional
N/A
N/A
2R
2R
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Virtex-II DCI
Reference
Resistor
VRN = VRP = R = Z
VRN = VRP = R = Z
VRN = VRP = R = Z
VRN = VRP = R = Z
0
0
0
0
Recommended
50 Ω
50 Ω
50 Ω
50 Ω
(1)
Z
0
DS031_65a_100201
Note:
1. Z is the recommended PCB trace impedance.
0
Figure 11: HSTL DCI Usage Examples
DS031-2 (v3.5) November 5, 2007
Product Specification
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