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DLC10 参数 Datasheet PDF下载

DLC10图片预览
型号: DLC10
PDF下载: 下载PDF文件 查看货源
内容描述: 平台电缆USB II [Platform Cable USB II]
分类和应用:
文件页数/大小: 35 页 / 3444 K
品牌: XILINX [ XILINX, INC ]
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Platform Cable USB II  
X-Ref Target - Figure 30  
(A)  
(B)  
(C)  
(D)  
(E)  
12 Mb/s Bus Speed  
12 Mb/s Bus Speed  
480 Mb/s Bus Speed  
480 Mb/s Bus Speed  
480 Mb/s Bus Speed  
1.X Root Hub  
1.X Root Hub  
2.0 Root Hub  
2.0 Root Hub  
2.0 Root Hub  
500  
mA  
500  
mA  
500  
mA  
500  
mA  
500  
mA  
Power  
Power  
2.0 External  
Bus-Powered  
Hub  
2.0 External  
Self-Powered  
Hub  
2.0 External  
Self-Powered  
Hub  
Platform Cable  
USB II  
Platform Cable  
USB II  
Enumerates at  
full speed because  
root hub only  
Enumerates at  
Hi-Speed — best  
performance due to  
high bus speed.  
< 500  
mA  
< 500  
mA  
500  
mA  
operates at full  
speed — degraded  
performance due  
to slow bus speed  
Platform Cable  
USB II  
Platform Cable  
USB II  
Platform Cable  
USB II  
Enumerates at  
full speed because  
root hub only  
Enumerates at full speed  
because 2.0 external  
hub operates at full  
speed — degraded  
performance due to slow  
bus speed. Cable may  
not enumerate.  
Enumerates at  
Hi-Speed — best  
performance due to  
high bus speed.  
operates at full  
speed — degraded  
performance due  
to slow bus speed  
DS593_30_021408  
Figure 30: Platform Cable USB II Performance with Various Hub Types  
Interface Pin Descriptions  
Table 6: JTAG/SPI/Slave Serial Port: 2-mm Connector Signals  
MODE  
SPI  
Pin  
Number  
Direction(2)  
Description  
JTAG  
Slave-Serial  
Configuration Programming(1) Configuration  
Target Reference Voltage(3). This pin  
should be connected to a voltage bus on the  
target system that serves the JTAG, SPI or  
Slave Serial interface. For example, when  
programming a CoolRunner-II device using  
JTAG, VREF should be connected to the  
target VAUX bus.  
2
VREF  
VREF  
VREF  
In  
JTAG Test Mode Select. This pin is the  
JTAG mode signal establishing appropriate  
TAP state transitions for target ISP devices  
sharing the same data stream.  
4
TMS  
Out  
JTAG Test Clock. This pin is the clock  
signal for JTAG operations and should be  
connected to the TCK pin on all target ISP  
devices sharing the same data stream.  
6
8
TCK  
TDO  
Out  
In  
JTAG Test Data Out. This pin is the serial  
data stream received from the TDO pin on  
the last device in a JTAG chain.  
DS593 (v1.2.1) March 17, 2011  
www.xilinx.com  
29  
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