R
QPro Virtex 2.5V Radiation Hardened FPGAs
Table 3: CQFP Package (CB228) (Continued)
Table 4: Pinout Diagram Symbols (Continued)
Function
Pin #
Bank #
Symbol
Pin Function
GND
1, 8, 14, 27, 42,
48, 56, 66, 72,
86, 100, 106,
113, 123, 129,
143, 157, 163,
173, 180, 186,
200, 215, 221
-
v
Device-dependent V , n/c on smaller
devices
CCINT
O
R
r
V
V
CCO
REF
Device-dependent V , remains I/O on
REF
smaller devices
V
15, 30, 41, 73,
83, 99, 130,
140, 156, 187,
203, 214
-
-
CCINT
G
Ground
Ø, 1, 2, 3
❿, ❿,❿❿
Global Clocks
M0, M1, M2
V
18, 28, 37, 58,
76, 85, 95, 115,
133, 142, 152,
171, 191, 201,
210, 228
CCO
❿, ❿, ❿, ❿, D0/DIN, D1, D2, D3, D4, D5, D6, D7
❿, ❿, ❿, ❿
B
D
P
I
DOUT/BUSY
DONE
Pinout Diagrams
PROGRAM
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Table 4 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
INIT
K
W
S
T
+
–
CCLK
WRITE
Table 4: Pinout Diagram Symbols
CS
Symbol
Pin Function
Boundary-scan test access port
Temperature diode, anode
Temperature diode, cathode
No connect
S
d
General I/O
Device-dependent general I/O, n/c on
smaller devices
n
V
V
CCINT
10
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DS028 (v1.2) November 5, 2001
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Preliminary Product Specification
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