R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Output Flip-Flop, Clock to Out(1,2,3)
-3
Max
8.6
9.8
11.3
-
-1
Max
-
All
Min
Symbol
Description
Device
Units
ns
(4)
T
Global low skew clock to output using OFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
All Devices
1.5
2.0
2.3
2.5
3.0
ICKOF
-
ns
-
ns
9.5
3.0
ns
T
For output SLOW option add
3.0
ns
SLOW
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
3. Output timing is measured at ~50% V threshold with 50 pF external capacitive load.
CC
4. OFF = Output Flip-Flop
Output Flip-Flop, Clock to Out, BUFGEs 1, 2, 5, and 6
-3
Max
7.4
8.1
9.9
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Global early clock to output using OFF
Values are for BUFGEs 1, 2, 5, and 6.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.3
1.2
1.2
1.3
-
-
ICKEOF
ns
-
ns
8.5
ns
Notes:
1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% V threshold with 50 pF external capacitive load.
CC
DS029 (v1.3) June 25, 2000
www.xilinx.com
11
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
