R
QPRO XQ4000XL Series QML High-Reliability FPGAs
CLB Switching Characteristics (Continued)
-3
-1
Symbol
Description
Min
Max
Min
Max
Units
Hold Time After Clock K
T
F/G inputs
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
CKI
T
F/G inputs via H
CKIH
T
T
T
C inputs via SR/H0 through H
C inputs via H1 through H
CKHH0
CKHH1
CKHH2
C inputs via D /H2 through H
IN
T
C inputs via D /H2
CKDI
IN
T
C inputs via EC
CKEC
T
C inputs via SR, going Low (inactive)
CKR
Clock
T
Clock High time
Clock Low time
3.0
3.0
-
-
2.5
2.5
-
-
ns
ns
CH
T
CL
Set/Reset Direct
T
Width (High)
3.0
-
-
2.5
-
-
ns
ns
RPW
T
Delay from C inputs via S/R, going High to Q
3.7
2.8
RIO
Global Set/Reset
T
Minimum GSR pulse width
-
19.8
-
15.0
ns
MRW
T
Delay from GSR input to any Q
Toggle frequency (MHz) (for export control)
See page 17 for T
values per device.
RRI
MRQ
F
-
166
-
200
MHz
TOG
DS029 (v1.3) June 25, 2000
www.xilinx.com
7
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
