QPRO XQ4000XL Series QML High-Reliability FPGAs
R
XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and are expressed in nano-
seconds unless otherwise noted.
Single-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
Symbol
Write Operation
-1
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
6.8
8.1
-
-
1.6
2.7
-
-
Min
7.7
7.7
3.9
3.9
1.7
1.7
0
0
1.7
2.1
0
0
1.6
1.5
0
0
-
-
2.6
3.8
-
-
0.9
1.7
Max
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5.8
6.9
-
-
1.3
2.2
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Single Port RAM
Address write cycle time (clock K period)
Size
16x2
32x1
Min
9.0
9.0
4.5
4.5
2.2
2.2
0
0
2.0
2.5
0
0
2.0
1.8
0
0
-
-
4.5
6.5
-
-
1.1
2.2
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
AHS
T
AHTS
T
DSS
T
DSTS
T
DHS
T
DHTS
T
WSS
T
WSTS
T
WHS
T
WHTS
T
WOS
T
WOTS
Clock K pulse width (active edge)
16x2
32x1
Address setup time before clock K
16x2
32x1
Address hold time after clock K
16x2
32x1
D
IN
setup time before clock K
D
IN
hold time after clock K
WE setup time before clock K
16x2
32x1
16x2
32x1
16x2
32x1
WE hold time after clock K
16x2
32x1
Data valid after clock K
16x2
32x1
Read Operation
T
RC
T
RCT
T
ILO
T
IHO
T
ICK
T
IHCK
Address read cycle time
16x2
32x1
Data valid after address change (no Write Enable)
16x2
32x1
Address setup time before clock K
16x2
32x1
8
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
XILINX [ XILINX, INC ]
