R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Output Flip-Flop, Clock to Out, BUFGEs 3, 4, 7, and 8
-3
Max
8.8
9.7
10.9
-
-1
All
Min
Symbol
Description
Device
Max
Units
ns
T
Global early clock to output using OFF
Values are for BUFGEs 3, 4, 7, and 8.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.8
1.8
2.0
2.2
-
-
ICKEOF
ns
-
ns
9.3
ns
Notes:
1. Clock-to-out minimum delay is measured with the fastest route and the lightest load, Clock-to-out maximum delay is measured using
the farthest distance and a reference load of one clock pin (IK or OK) per IOB as well as driving all accessible CLB flip-flops. For
designs with a smaller number of clock loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can
be added to the AC parameter Tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for FAST mode
configurations.
2. Output timing is measured at ~50% V threshold with 50 pF external capacitive load.
CC
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
3
2
and load capacitance. It allows a user to adjust the specified
output delay if the load capacitance is different than 50 pF.
For example, if the actual load capacitance is 120 pF, add
2.5 ns to the specified delay. If the load capacitance is
20 pF, subtract 0.8 ns from the specified output delay.
1
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
slew rate control.
0
-1
-2
0
20
40
60
80
100
120
140
Capacitance (pF)
DS029_03_011300
Figure 1: Delay Factor at Various Capacitive Loads
12
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
XILINX [ XILINX, INC ]
