R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values are expressed in nanosec-
onds unless otherwise noted.
Global Low Skew Clock, Input Setup and Hold Times(1,2)
-3
-1
(1)
Symbol
No Delay
/T
Description
Device
Min
Min
Units
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 3.2
1.2 / 5.5
1.2 / 7.0
-
-
ns
ns
ns
ns
PSN PHN
(4)
Global early clock and FCL
-
-
0.9 / 7.1
Partial Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.1 / 0.0
6.4 / 1.0
6.7 / 1.2
-
-
ns
ns
ns
ns
PSP PHP
(4)
Global early clock and FCL
-
-
9.8 / 1.2
Full Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
6.6 / 0.0
6.8 / 0.0
-
-
ns
ns
ns
ns
PSD PHD
-
-
9.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
DS029 (v1.3) June 25, 2000
www.xilinx.com
13
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
