R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL(1,2)
-3
-1
Symbol
No Delay
Description
Device
Min
Min
(3)
T
/T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
PSEN PHEN
(4)
T
/T
Global early clock and FCL
-
PFSEN PFHEN
-
0.9 / 6.6
Partial Delay
(3)
T
/T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
7.0 / 0.8
9.0 / 0.8
-
-
PSEPN PHEP
(4)
T
/T
Global early clock and FCL
-
PFSEP PFHEP
-
11.0 / 0.0
Full Delay
/T
(3)
T
Global early clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
12.0 / 0.0
13.8 / 0.0
13.1 / 0.0
-
-
PSEPD PHED
-
-
13.6 / 0.0
Notes:
1. The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
2. Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
3. IFF = Input Flip-Flop or Latch
4. FCL = Fast Capture Latch
14
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
