R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
-3
-1
Symbol
Clocks
Description
Device
Min
Max
Min
Max
Units
T
T
Clock enable (EC) to clock (IK)
All devices
All devices
0.1
2.2
-
-
0.1
1.6
-
-
ns
ns
ECIK
OKIK
Delay from FCL enable (OK) active edge to IFF
clock (IK) active edge
Setup Times
Pad to clock (IK), no delay
T
All devices
1.7
2.3
-
-
1.3
1.8
-
-
ns
ns
PICK
T
Pad to clock (IK), via transparent fast capture latch, All devices
no delay
PICKF
T
Pad to fast capture latch enable (OK), no delay
Hold Times
All Hold Times
Global Set/Reset
All devices
1.2
0
-
-
0.9
0
-
-
ns
ns
POCK
All devices
T
Minimum GSR pulse width
All devices
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
-
-
-
-
-
19.8
15.9
22.5
29.1
-
-
-
-
-
-
15.0
ns
ns
ns
ns
ns
MRW
(2)
T
Delay from GSR input to any Q
-
RRI
-
-
26.0
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
T
All devices
All devices
-
-
-
1.6
3.1
3.7
-
-
-
1.7
2.4
2.8
ns
ns
ns
PID
T
PLI
T
Pad to I1, I2 via transparent FCL and input latch, no All devices
delay
PFLI
T
Clock (IK) to I1, I2 (flip-flop)
All devices
All devices
All devices
-
-
-
1.7
1.8
3.6
-
-
-
1.3
1.4
2.7
ns
ns
ns
IKRI
T
Clock (IK) to I1, I2 (latch enable, active Low)
IKLI
T
FCL enable (OK) active edge to I1, I2
(via transparent standard input latch)
OKLI
Notes:
1. IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
2. Indicates Minimum Amount of Time to Assure Valid Data.
16
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
XILINX [ XILINX, INC ]
