R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000XL devices and expressed in nanosec-
onds unless otherwise noted.
CLB Switching Characteristics
-3
-1
Symbol
Description
Min
Max
Min
Max
Units
Combinatorial Delays
T
F/G inputs to X/Y outputs
-
-
-
-
-
-
-
1.6
2.7
2.9
2.5
2.4
2.5
1.5
-
-
-
-
-
-
-
1.3
2.2
2.2
2.0
1.9
2.0
1.1
ns
ns
ns
ns
ns
ns
ns
ILO
IHO
T
F/G inputs via H’ to X/Y outputs
T
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
ITO
T
HH0O
HH1O
HH2O
CBYP
T
T
T
C inputs via D /H2 via H to X/Y outputs
IN
C inputs via EC, D /H2 to YQ, XQ output (bypass)
IN
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
T
-
-
-
-
-
-
2.7
3.3
-
-
-
-
-
-
2.0
2.5
ns
ns
ns
ns
ns
ns
OPCY
OUT
T
Add/subtract input (F3) to C
OUT
ASCY
T
Initialization inputs (F1, F3) to C
2.0
1.5
INCY
OUT
T
C
C
through function generators to X/Y outputs
2.8
2.4
SUM
IN
IN
T
T
to C
, bypass function generators
OUT
0.26
0.32
0.20
0.25
BYP
NET
Carry net delay, C
to C
IN
OUT
Sequential Delays
T
Clock K to flip-flop outputs Q
Clock K to latch outputs Q
-
-
2.1
2.1
-
-
1.6
1.6
ns
ns
CKO
T
CKLO
Setup Time Before Clock K
T
F/G inputs
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
-
-
-
-
-
-
-
-
-
-
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ICK
T
F/G inputs via H
IHCK
T
T
T
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
HH0CK
HH1CK
HH2CK
T
C inputs via D
IN
DICK
T
C inputs via EC
ECCK
T
C inputs via S/R, going Low (inactive)
RCK
CCK
T
C
C
input via F/G
IN
IN
T
input via F/G and H
CHCK
6
www.xilinx.com
DS029 (v1.3) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
