R
QPRO XQ4000XL Series QML High-Reliability FPGAs
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
-3
-1
(1)
Symbol
Dual Port RAM
Size
Min Max Min Max Units
Write Operation
T
T
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
9.0
4.5
2.5
0
7.7
3.9
1.7
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
-
-
T
-
-
ASDS
T
-
-
AHDS
T
T
D
D
setup time before clock K
hold time after clock K
2.5
0
-
2.0
0
-
DSDS
DHDS
WSDS
WHDS
WODS
IN
IN
-
-
-
-
T
T
T
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
1.8
0
1.6
0
-
-
-
7.8
-
6.7
DS029 (v1.3) June 25, 2000
www.xilinx.com
9
Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
