R
QPRO XQ4000XL Series QML High-Reliability FPGAs
CLB Switching Characteristics
(Continued)
-3
Symbol
Hold Time After Clock K
-1
Max
-
-
-
-
-
-
-
-
-
-
-
3.7
19.8
166
Min
0
0
0
0
0
0
0
0
2.5
2.5
2.5
-
-
-
Max
-
-
-
-
-
-
-
-
-
-
-
2.8
15.0
200
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
Description
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via D
IN
/H2 through H
C inputs via D
IN
/H2
C inputs via EC
C inputs via SR, going Low (inactive)
Clock High time
Clock Low time
Width (High)
Min
0
0
0
0
0
0
0
0
3.0
3.0
3.0
-
-
-
T
CKI
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
Clock
T
CH
T
CL
T
RPW
Set/Reset Direct
Delay from C inputs via S/R, going High to Q
T
RIO
Global Set/Reset
T
MRW
Minimum GSR pulse width
T
MRQ
F
TOG
Delay from GSR input to any Q
Toggle frequency (MHz) (for export control)
See
for T
RRI
values per device.
DS029 (v1.3) June 25, 2000
Product Specification
1-800-255-7778
7
XILINX [ XILINX, INC ]
