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59629851301NXB 参数 Datasheet PDF下载

59629851301NXB图片预览
型号: 59629851301NXB
PDF下载: 下载PDF文件 查看货源
内容描述: QML高可靠性的FPGA [QML High-Reliability FPGAs]
分类和应用:
文件页数/大小: 22 页 / 169 K
品牌: XILINX [ XILINX, INC ]
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R
QPRO XQ4000XL Series QML High-Reliability FPGAs  
XQ4000XL IOB Output Switching Characteristic Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
These path delays, provided as a guideline, have been  
extracted from the static timing analyzer report. All timing  
parameters assume worst-case operating conditions (sup-  
ply voltage and junction temperature). For Propagation  
Delays, slew-rate = fast unless otherwise noted. Values are  
expressed in nanoseconds unless otherwise noted.  
-3  
-1  
Symbol  
Clocks  
Description  
Min  
Max  
Min  
Max  
Units  
T
Clock High  
Clock Low  
3.0  
3.0  
-
-
2.5  
2.5  
-
-
ns  
ns  
CH  
T
CL  
Propagation Delays  
T
Clock (OK) to pad  
Output (O) to pad  
-
-
-
-
-
-
5.0  
4.1  
4.4  
4.1  
5.5  
5.1  
-
-
-
-
-
-
3.8  
3.1  
3.0  
3.3  
4.2  
3.9  
ns  
ns  
ns  
ns  
ns  
ns  
OKPOF  
T
OPF  
T
High-Z to pad High-Z (slew-rate independent)  
High-Z to pad active and valid  
TSHZ  
T
TSONF  
T
Output (O) to pad via fast output MUX  
Select (OK) to pad via fast MUX  
OFPF  
T
OKFPF  
Setup and Hold Times  
T
Output (O) to clock (OK) setup time  
Output (O) to clock (OK) hold time  
0.5  
0
-
-
-
-
0.3  
0
-
-
-
-
ns  
ns  
ns  
ns  
OOK  
T
OKO  
T
T
Clock Enable (EC) to clock (OK) setup time  
Clock Enable (EC) to clock (OK) hold time  
0
0
ECOK  
OKEC  
0.3  
0.1  
Global Set/Reset  
T
Minimum GSR pulse width  
Delay from GSR input to any pad  
XQ4013XL  
19.8  
-
15.0  
-
ns  
MRW  
(2)  
T
RPO  
-
-
-
-
20.5  
27.1  
33.7  
-
-
-
-
-
ns  
ns  
ns  
ns  
XQ4036XL  
-
-
XQ4062XL  
XQ4085XL  
29.5  
Slew Rate Adjustment  
For output SLOW option add  
T
-
3.0  
-
2.0  
ns  
SLOW  
Notes:  
1. Output timing is measured at ~50% V threshold, with 50 pF external capacitive loads.  
CC  
2. Indicates Minimum Amount of Time to Assure Valid Data.  
DS029 (v1.3) June 25, 2000  
www.xilinx.com  
17  
Product Specification  
1-800-255-7778