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5962-9957401NUX 参数 Datasheet PDF下载

5962-9957401NUX图片预览
型号: 5962-9957401NUX
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文件页数/大小: 31 页 / 249 K
品牌: XILINX [ XILINX, INC ]
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R
QPro Virtex 2.5V QML High-Reliability FPGAs  
Table 3: Virtex QFP Package Pinout Information (Continued)  
Pin Name  
Device  
XQV100  
XQV300  
XQV600  
PQ/HQ240  
... + 229  
... + 236  
... + 230  
VREF, Bank 0  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
VREF, Bank 1  
XQV100  
XQV300  
XQV600  
... + 194  
... + 187  
... + 193  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
VREF, Bank 2  
XQV100  
XQV300  
XQV600  
... + 168  
... + 175  
... + 169  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
VREF, Bank 3  
XQV100  
XQV300  
XQV600  
... + 133  
... + 126  
... + 132  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
VREF, Bank 4  
XQV100  
XQV300  
XQV600  
... + 108  
... + 115  
... + 109  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
VREF, Bank 5  
XQV100  
XQV300  
XQV600  
... + 73  
... + 66  
... + 72  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
VREF, Bank 6  
XQV100  
XQV300  
XQV600  
... + 47  
... + 54  
... + 48  
(VREF pins are listed incrementally. Connect all pins listed for both  
the required device and all smaller devices listed in the same  
package.)  
Within each bank, if input reference voltage is not required, all VREF  
pins are general I/O.  
18  
www.xilinx.com  
DS002 (v1.5) December 5, 2001  
1-800-255-7778  
Preliminary Product Specification  
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