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5962-9957401NUX 参数 Datasheet PDF下载

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型号: 5962-9957401NUX
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品牌: XILINX [ XILINX, INC ]
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R
QPro Virtex 2.5V QML High-Reliability FPGAs  
Virtex Pin-to-Pin Input Parameter Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Listed below are representative  
values for typical pin locations and normal clock loading.  
Values are expressed in nanoseconds unless otherwise  
noted  
Global Clock Setup and Hold for LVTTL Standard, with DLL  
Speed Grade  
-4  
Symbol  
Description  
Device  
Min  
Max  
Units  
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different  
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.  
No Delay  
TPSDLL/TPHDLL  
XQV100  
XQV300  
XQV600  
XQV1000  
2.1 / 0.4  
2.1 / 0.4  
2.1 / 0.4  
2.1 / 0.4  
-
-
-
-
ns  
ns  
ns  
ns  
Global clock and IFF, with DLL  
Notes:  
1. IFF = Input Flip-Flop or Latch  
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured  
relative to the Global Clock input signal with the slowest route and heaviest load.  
3. DLL output jitter is already included in the timing calculation.  
Global Clock Setup and Hold for LVTTL Standard, without DLL  
Speed Grade  
-4  
Symbol  
Description  
Device  
Min  
Max  
Units  
Input Setup and Hold Time Relative to Global Clock Input Signal for LVTTL Standard. For data input with different  
standards, adjust the setup time delay by the values shown in Input Delay Adjustments.  
Full Delay  
T
PSFD/TPHFD  
XQV100  
XQV300  
XQV600  
XQV1000  
3.0 / 0.0  
3.1 / 0.0  
3.3 / 0.0  
3.6 / 0.0  
-
-
-
-
ns  
ns  
ns  
ns  
Global clock and IFF, without DLL  
Notes:  
1. IFF = Input Flip-Flop or Latch  
2. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured  
relative to the Global Clock input signal with the slowest route and heaviest load.  
3. A Zero 0Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed best-case, but  
if a 0is listed, there is no positive hold time.  
DS002 (v1.5) December 5, 2001  
www.xilinx.com  
15  
Preliminary Product Specification  
1-800-255-7778  
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