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5962-9957401NUX 参数 Datasheet PDF下载

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型号: 5962-9957401NUX
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文件页数/大小: 31 页 / 249 K
品牌: XILINX [ XILINX, INC ]
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R
QPro Virtex 2.5V QML High-Reliability FPGAs  
TBUF Switching Characteristics  
Speed Grade  
-4  
Symbol  
Description  
Min  
Max  
Units  
Combinatorial Delays  
TIO  
TOFF  
TON  
IN input to OUT output  
-
-
-
0.0  
0.2  
0.2  
ns  
ns  
ns  
TRI input to OUT output high-impedance  
Tri input to valid data on OUT output  
JTAG Test Access Port Switching Characteristics  
Speed Grade  
-4  
Symbol  
TTAPTCK  
TTCKTAP  
TTCKTDO  
FTCK  
Description  
TMS and TDI setup times before TCK  
Min  
4.0  
2.0  
-
Max  
-
Units  
ns  
TMS and TDI hold times after TCK  
Output delay from clock TCK to output TDO  
Maximum TCK clock frequency  
-
ns  
11.0  
33  
ns  
-
MHz  
Virtex Pin-to-Pin Output Parameter Guidelines  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Listed below are representative  
values for typical pin locations and normal clock loading.  
Values are expressed in nanoseconds unless otherwise  
noted.  
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL  
Speed Grade  
-4  
Symbol  
Description  
Device  
XQV100  
XQV300  
XQV600  
XQV1000  
Min  
Max  
3.6  
3.6  
3.6  
3.6  
Units  
ns  
LVTTL Global Clock Input to Output Delay using Output Flip-flop,  
12 mA, Fast Slew Rate, with DLL. For data output with different  
standards, adjust the delays with the values shown in "IOB Output  
Switching Characteristics Standard Adjustments" on page 8.  
-
-
-
-
ns  
ns  
ns  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and  
where all accessible IOB and CLB flip-flops are clocked by the global clock net.  
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For different loads, see Table 2.  
3. DLL output jitter is already included in the timing calculation.  
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL  
Speed Grade  
-4  
Symbol  
Description  
Device  
XQV100  
XQV300  
XQV600  
XQV1000  
Min  
Max  
5.7  
5.9  
6.0  
6.3  
Units  
ns  
LVTTL Global Clock Input to Output Delay using Output Flip-flop,  
12 mA, Fast Slew Rate, without DLL. For data output with different  
standards, adjust the delays with the values shown in "IOB Output  
Switching Characteristics Standard Adjustments" on page 8.  
-
-
-
-
ns  
ns  
ns  
Notes:  
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column,and  
where all accessible IOB and CLB flip-flops are clocked by the global clock net.  
2. Output timing is measured at 50% VCC threshold with 35 pF external capacitive load. For different loads, see Table 2.  
DS002 (v1.5) December 5, 2001  
www.xilinx.com  
13  
Preliminary Product Specification  
1-800-255-7778  
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