R
QPro Virtex 2.5V QML High-Reliability FPGAs
CLB SelectRAM Switching Characteristics
Speed Grade
-4
Symbol
Sequential Delays
TSHCKO
Description
Min
Max
Units
ns
Clock CLK to X/Y outputs (WE active)
Clock CLK to X/Y outputs
-
-
3.0
Shift-Register Mode
TSHCKO
3.0
ns
Setup Times before Clock CLK
Setup Time / Hold Time
TAS/TAH
TDS/TDH
F/G address inputs
0.7 / 0
0.9 / 0
1.0 / 0
-
-
-
ns
ns
ns
BX/BY data inputs (DIN)
CE input (WE)
T
WS/TWH
Shift-Register Mode
TSHDICK
BX/BY data inputs (DIN)
CE input (WS)
0.9
1.0
-
-
ns
ns
TSHCECK
Clock CLK
TWPH
Minimum pulse width, High
3.1
3.1
6.2
-
-
-
ns
ns
ns
TWPL
Minimum pulse width, Low
TWC
Minimum clock period to meet address write cycle time
Shift-Register Mode
TSRPH
Minimum pulse width, High
Minimum pulse width, Low
3.1
3.1
-
-
ns
ns
TSRPL
BLOCKRAM Switching Characteristics
Speed Grade
-4
Symbol
Description
Min
Max
Units
Sequential Delays
TBCKO
Clock CLK to DOUT output
-
4.1
ns
Setup Times Before Clock Clk
TBACK/TBCKA
BDCK/TBCKD
TBECK/TBCKE
BRCK/TBCKR
BWCK/TBCKW
ADDR inputs
DIN inputs
EN input
1.5 / 0
1.5 / 0
3.4 / 0
3.2 / 0
3.0 / 0
-
-
-
-
-
ns
ns
ns
ns
ns
T
T
RST input
WEN input
T
Clock CLK
TBPWH
Minimum pulse width, High
Minimum pulse width, Low
2.0
2.0
4.0
-
-
-
ns
ns
ns
TBPWL
TBCCS
CLKA -> CLKB setup time for different ports
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
12
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
XILINX [ XILINX, INC ]
