R
QPro Virtex 2.5V QML High-Reliability FPGAs
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Symbol
Description
Standard
-4
Units
Output Delay Adjustments
TOLVTTL_S2 Standard-specific adjustments for output delays
LVTTL, slow
2 mA
4 mA
17.0
8.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
terminating at pads (based on standard capacitive
load, Csl)
TOLVTTL_S4
TOLVTTL_S6
TOLVTTL_S8
TOLVTTL_S12
TOLVTTL_S16
TOLVTTL_S24
TOLVTTL_F2
TOLVTTL_F4
TOLVTTL_F6
TOLVTTL_F8
TOLVTTL_F12
TOLVTTL_F16
TOLVTTL_F24
TOLVCMOS2
TOPCI33_3
TOPCI33_5
TOGTL
6 mA
5.6
8 mA
3.5
12 mA
16 mA
24 mA
2 mA
2.2
2.0
1.6
LVTTL, fast
15.1
6.1
4 mA
6 mA
3.6
8 mA
1.2
12 mA
16 mA
24 mA
0.0
–0.05
–0.23
0.12
2.7
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
GTL
3.3
0.6
TOGTLP
GTL+
1.0
TOHSTL_I
HSTL I
–0.5
–1.0
–1.1
–0.5
–1.0
–0.5
–1.1
–0.6
–1.0
TOHSTL_III
TOHSTL_IV
TOSSTL2_I
TOSSTL2_II
TOSSTL3_I
TOSSTL3_II
TOCTT
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
TOAGP
AGP
8
www.xilinx.com
1-800-255-7778
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
XILINX [ XILINX, INC ]
