R
QPro Virtex 2.5V QML High-Reliability FPGAs
Recommended Operating Conditions
Symbol
V
CCINT
V
CCO
T
IN
T
IC
Description
Supply voltage relative to GND, T
C
= –55°C to +125°C
Supply voltage relative to GND, T
J
= –55°C to +125°C
Supply voltage relative to GND, T
C
= –55°C to +125°C
Supply voltage relative to GND, T
J
= –55°C to +125°C
Input signal transition time
Initialization Temperature Range
(4)
XQVR300
XQVR600
XQVR1000
T
OC
Operational Temperature Range
(5)
XQVR300
XQVR600
XQVR1000
Ceramic packages
Plastic packages
Ceramic packages
Plastic packages
Min
2.5 – 5%
2.5 – 5%
1.2
1.2
-
–55
–55
–40
–55
–55
–55
Max
2.5 + 5%
2.5 + 5%
3.6
3.6
250
+125
+125
+125
+125
+125
+125
Units
V
V
V
V
ns
°C
°C
°C
°C
°C
°C
Notes:
1. Correct operation is guaranteed with a minimum V
CCINT
of 2.25V (Nominal V
CCINT
– 10%). Below the minimum value stated above,
all delay parameters increase by 3% for each 50 mV reduction in V
CCINT
below the specified range.
2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per
°
C.
3. Input and output measurement threshold is ~50% of V
CC
.
4. Initialization occurs from the moment of V
CC
ramp-up to the rising transition of the INIT pin.
5. The device is operational after the INIT pin has transitioned high.
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRIO
I
CCINTQ
Description
Data retention V
CCINT
voltage
(below which configuration data may be lost)
Data retention V
CCO
voltage
(below which configuration data may be lost)
Quiescent V
CCINT
supply current
(1)
Device
All
All
XQV100
XQV300
XQV600
XQV1000
I
CCOQ
Quiescent V
CCINT
supply current
(1)
XQV100
XQV300
XQV600
XQV1000
I
REF
I
L
C
IN
I
RPU
I
RPD
V
REF
current per V
REF
pin
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) at V
IN
= 0V, V
CCO
= 3.3V (sample tested)
Pad pull-down (when selected) at V
IN
= 3.6V (sample tested)
-
-
-
-
-
Min
2.0
1.2
-
-
-
-
-
-
-
-
-
–10
-
(2)
(2)
Max
-
-
50
75
100
100
2
2
2
2
20
+10
8
0.25
0.15
Units
V
V
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
pF
mA
mA
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
1-800-255-7778
3
XILINX [ XILINX, INC ]
