R
QPro Virtex 2.5V QML High-Reliability FPGAs
Minimum Clock to Out for Virtex Devices
With DLL
Without DLL
V600
6.1
I/O Standard
LVTTL_S2(1)
All Devices
5.2
3.5
2.8
2.2
2.0
1.9
1.8
2.9
1.7
1.2
1.1
1.0
0.9
0.9
1.1
1.5
1.4
1.6
1.7
1.1
0.9
0.8
0.9
0.8
0.8
0.7
1.0
1.0
V100
6.0
4.3
3.6
3.1
2.9
2.8
2.6
3.8
2.6
2.0
1.9
1.8
1.8
1.7
1.9
2.4
2.2
2.5
2.5
1.9
1.7
1.6
1.7
1.6
1.7
1.5
1.8
1.8
V300
6.1
4.4
3.7
3.1
2.9
2.8
2.7
3.8
2.6
2.1
2.0
1.9
1.8
1.8
2.0
2.4
2.3
2.5
2.6
2.0
1.8
1.7
1.8
1.7
1.7
1.6
1.9
1.9
V1000
6.1
4.4
3.7
3.2
3.0
2.9
2.8
3.9
2.7
2.2
2.0
1.9
1.9
1.9
2.1
2.5
2.4
2.6
2.7
2.0
1.9
1.8
1.8
1.7
1.8
1.7
2.0
2.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL_S4(1)
LVTTL_S6(1)
LVTTL_S8(1)
LVTTL_S12(1)
LVTTL_S16(1)
LVTTL_S24(1)
LVTTL_F2(1)
LVTTL_F4(1)
LVTTL_F6(1)
LVTTL_F8(1)
LVTTL_F12(1)
LVTTL_F16(1)
LVTTL_F24(1)
LVCMOS2
PCI33_3
4.4
3.7
3.2
3.0
2.9
2.7
3.9
2.7
2.1
2.0
1.9
1.8
1.8
2.0
2.5
PCI33_5
2.3
GTL
2.6
GTL+
2.6
HSTL I
2.0
HSTL III
1.8
HSTL IV
1.7
SSTL2 I
1.8
SSTL2 II
1.7
SSTL3 I
1.7
SSTL3 II
1.6
CTT
1.9
AGP
1.9
Notes:
1. S = Slow Slew Rate, F = Fast Slew Rate
2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column. and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
3. Output timing is measured at 50% VCC threshold with 8 pF external capacitive load.
14
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
XILINX [ XILINX, INC ]
