R
QPro Virtex 2.5V QML High-Reliability FPGAs
Recommended Operating Conditions
Symbol
Description
Min
Max
Units
V
VCCINT Supply voltage relative to GND, TC = –55°C to +125°C Ceramic packages
Supply voltage relative to GND, TJ = –55°C to +125°C Plastic packages
2.5 – 5% 2.5 + 5%
2.5 – 5% 2.5 + 5%
V
VCCO
Supply voltage relative to GND, TC = –55°C to +125°C Ceramic packages
Supply voltage relative to GND, TJ = –55°C to +125°C Plastic packages
Input signal transition time
1.2
1.2
-
3.6
V
3.6
V
TIN
TIC
250
ns
°C
°C
°C
°C
°C
°C
Initialization Temperature Range(4)
XQVR300
XQVR600
XQVR1000
XQVR300
XQVR600
XQVR1000
–55
–55
–40
–55
–55
–55
+125
+125
+125
+125
+125
+125
TOC
Operational Temperature Range(5)
Notes:
1. Correct operation is guaranteed with a minimum VCCINT of 2.25V (Nominal VCCINT – 10%). Below the minimum value stated above,
all delay parameters increase by 3% for each 50 mV reduction in VCCINT below the specified range.
2. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
3. Input and output measurement threshold is ~50% of VCC
.
4. Initialization occurs from the moment of VCC ramp-up to the rising transition of the INIT pin.
5. The device is operational after the INIT pin has transitioned high.
DC Characteristics Over Recommended Operating Conditions
Symbol
VDRINT Data retention VCCINT voltage
(below which configuration data may be lost)
Data retention VCCO voltage
(below which configuration data may be lost)
ICCINTQ Quiescent VCCINT supply current(1)
Description
Device
Min
Max
Units
All
2.0
-
V
VDRIO
All
1.2
-
V
XQV100
-
50
75
100
100
2
mA
mA
mA
mA
mA
mA
mA
mA
µA
XQV300
-
XQV600
-
XQV1000
-
ICCOQ
Quiescent VCCINT supply current(1)
XQV100
-
XQV300
-
2
XQV600
-
2
XQV1000
-
-
2
IREF
IL
VREF current per VREF pin
-
-
-
-
-
20
+10
8
Input or output leakage current
–10
µA
CIN
IRPU
IRPD
Input capacitance (sample tested)
-
pF
(2)
Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V (sample tested)
Pad pull-down (when selected) at VIN = 3.6V (sample tested)
0.25
0.15
mA
mA
(2)
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins in a High-Z state and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
DS002 (v1.5) December 5, 2001
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
