R
QPro Virtex 2.5V QML High-Reliability FPGAs
CLB Switching Characteristics
Delays originating at F/G inputs vary slightly according to the input used. The values listed below are worst-case. Precise
values are provided by the timing analyzer.
Speed Grade
-4
Symbol
Description
Min
Max
Units
Combinatorial Delays
TILO
TIF5
4-input function: F/G inputs to X/Y outputs
5-input function: F/G inputs to F5 output
5-input function: F/G inputs to X output
-
-
-
-
-
-
-
0.8
0.9
1.0
1.2
0.5
0.8
0.7
ns
ns
ns
ns
ns
ns
ns
TIF5X
TIF6Y
6-input function: F/G inputs to Y output via F6 MUX
6-input function: F5IN input to Y output
TF5INY
TIFNCTL
TBYYB
Incremental delay routing through transparent latch to XQ/YQ outputs
BY input to YB output
Sequential Delays
TCKO
FF clock CLK to XQ/YQ outputs
Latch clock CLK to XQ/YQ outputs
-
-
1.4
1.6
ns
ns
TCKLO
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
TICK/TCKI
4-input function: F/G Inputs
5-input function: F/G inputs
6-input function: F5IN input
6-input function: F/G inputs via F6 MUX
BX/BY inputs
1.5 / 0
1.7 / 0
1.2 / 0
1.9 / 0
0.8 / 0
1.0 / 0
0.9 / 0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
T
IF5CK/TCKIF5
T
F5INCK/TCKF5IN
IF6CK/TCKIF6
T
T
DICK/TCKDI
T
CECK/TCKCE
CE input
T
RCKTCKR
SR/BY inputs (synchronous)
Clock CLK
TCH
Minimum pulse width, High
Minimum pulse width, Low
2.0
2.0
-
-
ns
ns
TCL
Set/Reset
TRPW
Minimum pulse width, SR/BY inputs
3.3
-
ns
ns
ns
TRQ
Delay from SR/BY inputs to XQ/YQ outputs (asynchronous)
Delay from GSR to XQ/YQ outputs
-
-
1.4
12.5
TIOGSRQ
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
10
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
XILINX [ XILINX, INC ]
