R
QPro Virtex 2.5V QML High-Reliability FPGAs
Table 6: Pinout Diagram Symbols
Pinout Diagrams
Symbol
Pin Function
M0, M1, M2
The following diagrams illustrate the locations of spe-
cial-purpose pins on Virtex FPGAs. Table 6 lists the sym-
bols used in these diagrams. The diagrams also show
I/O-bank boundaries.
❿, ❿,❿❿
❿, ❿, ❿, ❿, D0/DIN, D1, D2, D3, D4, D5, D6, D7
❿, ❿, ❿, ❿
Table 6: Pinout Diagram Symbols
B
D
P
I
DOUT/BUSY
Symbol
Pin Function
General I/O
DONE
S
d
PROGRAM
Device-dependent general I/O, n/c on
smaller devices
INIT
V
v
VCCINT
K
W
S
T
+
–
CCLK
Device-dependent VCCINT, n/c on smaller
devices
WRITE
CS
O
R
r
VCCO
VREF
Boundary-scan test aAccess port
Temperature diode, anode
Temperature diode, cathode
No connect
Device-dependent VREF, remains I/O on
smaller devices
G
Ground
n
Ø, 1, 2, 3
Global Clocks
DS002 (v1.5) December 5, 2001
www.xilinx.com
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Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
