R
QPro Virtex 2.5V QML High-Reliability FPGAs
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in
Speed Grade
-4
Symbol
Propagation Delays
Description
Min
Max
Units
T
IOOP
T
IOOLP
3-State Delays
O input to pad
O input to pad via transparent latch
T input to pad high-impedance
(1)
T input to valid data on pad
T input to pad high-impedance via transparent latch
(1)
T input to valid data on pad via transparent latch
GTS to pad high-impedance
(1)
-
-
3.5
4.0
ns
ns
T
IOTHZ
T
IOTON
T
IOTLPHZ
T
IOTLPON
T
GTS
Sequential Delays
-
-
-
-
-
2.4
3.7
3.0
4.2
6.3
ns
ns
ns
ns
ns
T
IOCKP
T
IOCKHZ
T
IOCKON
T
IOOCK
/T
IOCKO
T
IOOCECK
/T
IOCKOCE
T
IOSRCKO
/T
IOCKOSR
T
IOTCK
/T
IOCKT
T
IOTCECK
/T
IOCKTCE
T
IOSRCKT
/T
IOCKTSR
Set/Reset Delays
Clock CLK to pad
Clock CLK to pad high-impedance (synchronous)
(1)
Clock CLK to valid data on pad (synchronous)
-
-
-
3.5
2.9
4.1
ns
ns
ns
Setup and Hold Times before/after Clock CLK
Setup Time / Hold Time
(2)
O input
OCE input
SR input (OFF)
3-state setup times, T input
3-state setup times, TCE input
3-state setup times, SR input (TFF)
1.3 / 0
1.0 / 0
1.4 / 0
0.9 / 0
1.1 / 0
1.3 / 0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
T
IOSRP
T
IOSRHZ
T
IOSRON
SR input to pad (asynchronous)
SR input to pad high-impedance (asynchronous)
(1)
SR input to valid data on pad (asynchronous)
4.6
3.9
5.1
-
-
-
ns
ns
ns
Notes:
1. High-impedance turn-off delays should not be adjusted.
2. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
1-800-255-7778
7
XILINX [ XILINX, INC ]
