R
QPro Virtex 2.5V QML High-Reliability FPGAs
Virtex Switching Characteristics
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Virtex devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for
LVTTL levels. For other standards, adjust the delays with
the values shown in
Speed Grade
-4
Symbol
Propagation Delays
Description
Device
Min
Max
Units
T
IOPI
T
IOPID
Pad to I output, no delay
Pad to I output, with delay
All
XQV100
XQV300
XQV600
XQV1000
-
-
-
-
-
-
-
-
-
-
1.0
1.9
1.9
2.3
2.7
2.0
4.8
5.1
5.5
5.9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
IOPLI
T
IOPLID
Pad to output IQ via transparent latch, no
delay
Pad to output IQ via transparent latch, with
delay
All
XQV100
XQV300
XQV600
XQV1000
Sequential Delays
T
IOCKIQ
T
IOPICK
/ T
IOICKP
T
IOPICKD
/ T
IOICKPD
T
IOICECK
/ T
IOCKICE
T
IOSRCKI
/ T
IOCKISR
Set/Reset Delays
Clock CLK to output IQ
All
-
0.8
ns
Setup and Hold Times with Respect to Clock CLK
Setup Time / Hold Time
Pad, no delay
Pad, with delay
ICE input
SR input (IFF, synchronous)
All
All
All
All
2.0 / 0
5.0 / 0
1.0 / 0
1.3 / 0
-
-
-
-
ns
ns
ns
ns
T
IOSRIQ
T
GSRQ
SR input to IQ (asynchronous)
GSR to output IQ
All
All
-
-
1.8
12.5
ns
ns
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”,
but if a “0” is listed, there is no positive hold time.
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
1-800-255-7778
5