QPro Virtex 2.5V QML High-Reliability FPGAs
R
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Speed Grade
Symbol
Output Delay Adjustments
Description
Standard
-4
Units
T
OLVTTL_S2
T
OLVTTL_S4
T
OLVTTL_S6
T
OLVTTL_S8
T
OLVTTL_S12
T
OLVTTL_S16
T
OLVTTL_S24
T
OLVTTL_F2
T
OLVTTL_F4
T
OLVTTL_F6
T
OLVTTL_F8
T
OLVTTL_F12
T
OLVTTL_F16
T
OLVTTL_F24
T
OLVCMOS2
T
OPCI33_3
T
OPCI33_5
T
OGTL
T
OGTLP
T
OHSTL_I
T
OHSTL_III
T
OHSTL_IV
T
OSSTL2_I
T
OSSTL2_II
T
OSSTL3_I
T
OSSTL3_II
T
OCTT
T
OAGP
Standard-specific adjustments for output delays
terminating at pads (based on standard capacitive
load, C
sl
)
LVTTL, slow
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
17.0
8.6
5.6
3.5
2.2
2.0
1.6
15.1
6.1
3.6
1.2
0.0
–0.05
–0.23
0.12
2.7
3.3
0.6
1.0
–0.5
–1.0
–1.1
–0.5
–1.0
–0.5
–1.1
–0.6
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL, fast
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
LVCMOS2
PCI, 33 MHz, 3.3V
PCI, 33 MHz, 5.0V
GTL
GTL+
HSTL I
HSTL III
HSTL IV
SSTL2 I
SSTL2 II
SSTL3 I
SSTL3 II
CTT
AGP
8
1-800-255-7778
DS002 (v1.5) December 5, 2001
Preliminary Product Specification
XILINX [ XILINX, INC ]
