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5962-9957201NZA 参数 Datasheet PDF下载

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型号: 5962-9957201NZA
PDF下载: 下载PDF文件 查看货源
内容描述: QPro的Virtex 2.5V QML高可靠性的FPGA [QPro Virtex 2.5V QML High-Reliability FPGAs]
分类和应用:
文件页数/大小: 31 页 / 249 K
品牌: XILINX [ XILINX, INC ]
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R
QPro Virtex 2.5V QML High-Reliability FPGAs  
Virtex Switching Characteristics  
Testing of switching parameters is modeled after testing  
methods specified by MIL-M-38510/605. All devices are  
100% functionally tested. Internal timing parameters are  
derived from measuring internal test patterns. Listed below  
are representative values. For more specific, more precise,  
and worst-case guaranteed data, use the values reported  
by the static timing analyzer (TRCE in the Xilinx Develop-  
ment System) and back-annotated to the simulation netlist.  
All timing parameters assume worst-case operating condi-  
tions (supply voltage and junction temperature). Values  
apply to all Virtex devices unless otherwise noted.  
IOB Input Switching Characteristics  
Input delays associated with the pad are specified for  
LVTTL levels. For other standards, adjust the delays with  
the values shown in "IOB Input Switching Characteristics  
Standard Adjustments" on page 6.  
Speed Grade  
-4  
Symbol  
Propagation Delays  
TIOPI  
Description  
Device  
Min  
Max  
Units  
Pad to I output, no delay  
All  
-
-
-
-
-
-
1.0  
1.9  
1.9  
2.3  
2.7  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
TIOPID  
Pad to I output, with delay  
XQV100  
XQV300  
XQV600  
XQV1000  
All  
TIOPLI  
Pad to output IQ via transparent latch, no  
delay  
TIOPLID  
Pad to output IQ via transparent latch, with  
delay  
XQV100  
XQV300  
XQV600  
XQV1000  
-
-
-
-
4.8  
5.1  
5.5  
5.9  
ns  
ns  
ns  
ns  
Sequential Delays  
TIOCKIQ  
Clock CLK to output IQ  
All  
-
0.8  
ns  
Setup and Hold Times with Respect to Clock CLK  
Setup Time / Hold Time  
TIOPICK / TIOICKP  
Pad, no delay  
All  
All  
All  
All  
2.0 / 0  
5.0 / 0  
1.0 / 0  
1.3 / 0  
-
-
-
-
ns  
ns  
ns  
ns  
T
IOPICKD / TIOICKPD  
IOICECK / TIOCKICE  
IOSRCKI / TIOCKISR  
Pad, with delay  
ICE input  
T
T
SR input (IFF, synchronous)  
Set/Reset Delays  
TIOSRIQ  
SR input to IQ (asynchronous)  
GSR to output IQ  
All  
All  
-
-
1.8  
ns  
ns  
TGSRQ  
12.5  
Notes:  
1. A Zero 0Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed best-case,  
but if a 0is listed, there is no positive hold time.  
DS002 (v1.5) December 5, 2001  
www.xilinx.com  
5
Preliminary Product Specification  
1-800-255-7778  
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