R
QPro Virtex 2.5V QML High-Reliability FPGAs
DLL Timing Parameters
Switching parameters testing is modeled after testing meth-
ods specified by MIL-M-38510/605; all devices are 100 per-
cent functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
ters are derived from benchmark timing patterns. The fol-
lowing guidelines reflect worst-case values across the
recommended operating conditions.
Speed Grade -4
Symbol
FCLKINHF
FCLKINLF
TDLLPWHF
TDLLPWLF
Description
Input clock frequency (CLKDLLHF)
Min
60
Max
180
90
-
Units
MHz
MHz
ns
Inputclock frequency (CLKDLL)
Input clock pulse width (CLKDLLHF)
Input clock pulse width (CLKDLL)
25
2.4
3.0
-
ns
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
CLKDLLHF
Min Max
1.0
CLKDLL
Symbol
TIPTOL
TIJITCC
TLOCK
Description
Input clock period tolerance
Min
Max
1.0
Units
ns
-
-
-
Input clock jitter cycle to cycle
Time required for DLL to acquire Lock
FCLKIN
-
±150
±300
ps
> 60 MHz
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
-
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
20
25
µs
µs
µs
µs
µs
ps
ps
ps
-
-
-
50
90
-
120
±150
±100
±60
TSKEW
DLL output skew (between any DLL output)
±150
±100
±60
TOPHASE DLL output long term phase differential
TOJITCC DLL output ditter cycle to cycle
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to +100°C).
Period Tolerance: the allowed input clock period change in nanoseconds.
+ T
_
T
T
IPTOL
CLKIN
CLKIN
Clock Jitter: the difference between an ideal reference clock edgfe and the actual design.
_
+
DS002_01_060100
T
OJITCC
Figure 1: Frequency Tolerance and Clock Jitter
16
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
XILINX [ XILINX, INC ]
