R
QPro Virtex 2.5V QML High-Reliability FPGAs
Table 1: QPro Virtex Field-Programmable Gate Array Family Members
Maximum
Available I/O
Max Select
RAM Bits
Device
XQV100
XQV300
XQV600
XQV1000
System Gates CLB Array
Logic Cells
2,700
Block RAM Bits
40,960
108,904
322,970
661,111
1,124,022
20 x 30
32 x 48
48 x 72
64 x 96
180
316
316
404
38,400
98,304
6,912
65,536
15,552
27,648
98,304
221,184
393,216
131,072
Virtex Electrical Characteristics
Based on preliminary characterization. Further changes are not expected.
All specifications are representative of worst-case supply voltage and junction temperature conditions. The parameters
included are common to popular designs and typical applications. Contact the factory for design considerations requiring
more detailed information.
Virtex DC Characteristics
Absolute Maximum Ratings
Symbol
VCCINT
VCCO
Description
Min/Max
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
Units
V
Supply voltage relative to GND
Supply voltage relative to GND
Input reference Voltage
V
VREF
V
(3)
VIN
Input voltage relative to GND
Using VREF
V
Internal threshold
V
VTS
VCC
TSTG
TJ
Voltage applied to 3-state output
V
Longest supply voltage rise time from 1V to 2.375V
Storage temperature (ambient)
ms
°C
°C
°C
–65 to +150
+150
Junction temperature
Ceramic packages
Plastic packages
+125
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Power supplies may turn on in any order.
3. For protracted periods (e.g., longer than a day), VIN should not exceed VCCO by more that 3.6V.
2
www.xilinx.com
DS002 (v1.5) December 5, 2001
1-800-255-7778
Preliminary Product Specification
XILINX [ XILINX, INC ]
