R
XC3000 Series Field Programmable Gate Arrays
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. For
example, the XC3020A has 64 such blocks arranged in 8
rows and 8 columns. The development system is used to
compile the configuration data which is to be loaded into
the internal configuration memory to define the operation
and interconnection of each block. User definition of CLBs
and their interconnecting networks may be done by auto-
matic translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the asyn-
chronous RD which, when enabled and High, is dominant
over clocked inputs. All flip-flops are reset by the
active-Low chip input, RESET, or during the configuration
process. The flip-flops share the enable clock (EC) which,
when Low, recirculates the flip-flops’ present states and
inhibits response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control inputs
and select their sources. The user may also select the
clock net input (K), as well as its active sense within each
CLB. This programmable inversion eliminates the need to
route both phases of a clock signal throughout the device.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
DI
DATA IN
0
MUX
1
D
Q
F
DIN
G
QX
F
RD
QX
X
A
F
7
B
COMBINATORIAL
FUNCTION
C
D
E
LOGIC
VARIABLES
CLB OUTPUTS
G
G
QY
Y
F
QY
DIN
G
0
MUX
D
Q
1
EC
ENABLE CLOCK
RD
1 (ENABLE)
K
CLOCK
RD
DIRECT
RESET
0 (INHIBIT)
(GLOBAL RESET)
X3032
Figure 5: Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program memory controlled multiplexer selection of
function. It has the following:
-
-
-
-
-
-
five logic variable inputs A, B, C, D, and E
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
November 9, 1998 (Version 3.1)
7-9
XILINX [ XILINX, INC ]
