R
XC3000 Series Field Programmable Gate Arrays
SPECIFIED WORST-CASE VALUES
1.00
0.80
TYPICAL COMMERCIAL
0.60
0.40
0.20
(+ 5.0 V, 25°C)
TYPICAL MILITARY
– 55
– 40
– 20
0
25
40
70
80
100
125
Figure 32: Relative Delay as a Function of TemperaTtuEMreP,ERSAuTpURpEly(°CV)oltage and Processing Variations
X6094
Power
Power Distribution
300
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
250
200
150
100
50
Inside the FPGA, a dedicated V
and ground ring sur-
CC
rounding the logic array provides power to the I/O drivers.
An independent matrix of V and groundlines supplies the
CC
XC3100A-3
XC3000A--6
interior logic of the device. This power distribution grid pro-
vides a stable supply and ground for all internal logic, pro-
viding the external package power pins are all connected
and appropriately decoupled. Typically a 0.1-µF capacitor
0
CLB Levels:
Gate Levels:
4 CLBs
(4-16)
3 CLBs
(3-12)
2 CLBs
(2-8)
1 CLB
(1-4)
Toggle
Rate
connected near the V and ground pins will provide ade-
CC
X7065
quate decoupling.
Figure 33: Clock Rate as a Function of Logic
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driv-
ing as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
Complexity (Number of Combinational Levels between
Flip-Flops)
7-36
November 9, 1998 (Version 3.1)
XILINX [ XILINX, INC ]
