R
XC3000 Series Field Programmable Gate Arrays
Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-
flows the lead device) on its DOUT pin. There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy-chain accepts data on the subsequent rising
CCLK edge.
*
If Readback is
Activated, a
+5 V
*
5-kΩ Resistor is
Required in
Series with M1
M0
M1
PWRDWN
Micro
Computer
5 kΩ
Optional
Daisy-Chained
LCAs with
Different
Configurations
STRB
D0
CCLK
DIN
M2
DOUT
HDC
D1
General-
Purpose
User I/O
Pins
I/O
Port
D2
D3
LDC
+5 V
FPGA
D4
D5
D6
D7
Other
I/O Pins
D/P
7
INIT
RESET
RESET
X5993
Figure 29: Slave Serial Mode Circuit Diagram
November 9, 1998 (Version 3.1)
7-31
XILINX [ XILINX, INC ]
