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5962-9561101MZC 参数 Datasheet PDF下载

5962-9561101MZC图片预览
型号: 5962-9561101MZC
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 190MHz, 320-Cell, CMOS, CQFP164, TOP BRAZED, CERAMIC, QFP-164]
分类和应用: 可编程逻辑
文件页数/大小: 76 页 / 730 K
品牌: XILINX [ XILINX, INC ]
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R
XC3000 Series Field Programmable Gate Arrays  
umn are connectable half-length lines. On the XC3020A  
and XC3120A FPGAs, only the outer Longlines are con-  
nectable half-length lines.  
Longlines  
The Longlines bypass the switch matrices and are intended  
primarily for signals that must travel a long distance, or  
must have minimum skew among multiple destinations.  
Longlines, shown in Figure 14, run vertically and horizon-  
tally the height or width of the interconnect area. Each inter-  
connection column has three vertical Longlines, and each  
interconnection row has two horizontal Longlines. Two  
additional Longlines are located adjacent to the outer sets  
of switching matrices. In devices larger than the XC3020A  
and XC3120A FPGAs, two vertical Longlines in each col-  
Longlines can be driven by a logic block or IOB output on a  
column-by-column basis. This capability provides a com-  
mon low skew control or clock line within each column of  
logic blocks. Interconnections of these Longlines are  
shown in Figure 15. Isolation buffers are provided at each  
input to a Longline and are enabled automatically by the  
development system when a connection is made.  
7
Figure 14: Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in  
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.  
November 9, 1998 (Version 3.1)  
7-15